1. Field of the Invention
This invention relates to a fabricating procedure of a semiconductor device, and more particularly to a fabricating procedure of a capacitor in a Dynamic Random Access Memory (DRAM).
2. Description of Related Art
For memory devices with high integration such as DRAM devices with memory capacity of 256 Megabit, their capacitor need a dielectric thin film to be constructed as the three dimensional structures like stacked type or trench type. Thus these memory devices should have a large area of the dielectric thin film to store the charge to avoid the soft error. Utilizing low pressure chemical vapor deposition (LPCVD), which is one of the chemical vapor deposition (CVD), to make the dielectric thin film of a material of Ta.sub.2 O.sub.5 is popular for the present because this material produces a dielectric constant about 25, which is far larger than that of a material of oxide, and has a better ability of step coverage. The step coverage means that the covering surface is kept in a step shape without being rounded.
In the design of a very large scale integration circuit (VLSI), to increase the capacitance in the integrated circuit (IC), it has three effective methods. The first is that the thickness of the dielectric thin film mediated between two electrodes is reduced because the capacitance is inversely proportional to the distance between these two electrodes. This method can increase the capacitance effectively but is difficult to be controlled to obtain a uniform and stable dielectric thin film. The second method is that the interfacial area between the dielectric thin film and the electrode is increased because the capacitance is proportional to the size of this area. For the present, to increase the size of the interfacial area, such as one of a fin type and a hemispheric grain type is applied but has a difficulty for massive production due to the complexity of fabrication. Another option is taking a cylindrical type. The third method is that the dielectric constant is increased such as the materials of Ta.sub.2 O.sub.5, Lead Zirconium Titanate (PZT) composed of Pb(Zr,Ti)O.sub.3, and Bismuth Strontium Titanate (BST) composed of (Ba,Sr)TiO.sub.3, which have high dielectric constant.
In the conventional method of fabricating a semiconductor device, a polysilicon material is usually to be taken for the electrodes of the capacitors. In this case, the higher the temperature is used in the process of annealing on the dielectric thin film, the lesser the defect exists in the dielectric thin film. This means the quality of the dielectric thin film should be better. But, if the temperatures used in the process of annealing is too high, a material of native oxide is easily produced around the interface between the dielectric thin film and the lower electrode to reduce the capacitance. Here, it doesn't happen around an interface between the dielectric thin film and an upper electrode because the upper interface has not been formed yet. On the contrary, if the temperatures used in the process of annealing is too low, and then the defect existing in the dielectric thin film would not effectively be removed.
Therefore, so far, to prevent the bad situations as described above, a metal layer, generally, is taken instead for the electrodes, which is usually made of a polysilicon layer in the conventional method. That is to say a Metal Insulator Metal (MIM) capacitor, which is especially applied in a Nonvolatile Ferroelectric Memory (FeRAM) and a DRAM with high integration.
The metal layer of the MIM capacitor is conventionally made of conductive material such as Platinum, Iridium, Iridium oxide or Ruthenium oxide. Unfortunately, using these materials for the MIM capacitor as the electrodes, it usually causes the bad quality of the profile of the electrode or the fence-like plate on the inner surface of the lower electrode. The fence-like plate being not easy to be removed is from the deposition of some remained reacting materials which are the products after the reaction of photoresist layer and the metal of the lower electrode during etching.
FIGS. 1-4 schematically illustrate the sectional plots of a capacitor in a DRAM in the conventional fabricating procedure. The like marks represent the like elements in the FIGS.
Referring to FIG. 1, a substrate 100 is provided, on which a number of field effect transistors in a DRAM are formed. One Field Effect Transistor (FET) includes a gate and an interchangeable source/drain region 106 on the active area. The neighboring FETs are isolated by a Field Oxide (FOX) 102 in between. Then, an insulating layer 108 is formed over the substrate 100 and is preferably including silicon dioxide by CVD. Then, the following is using the conventional technology of photolithography to define a contact window 109 on the insulating layer 108 and expose the interchangeable source/drain region 106 partly.
Then, an polysilicon layer 107 is deposited and fills the contact window 109 so that the polysilicon layer 107 is electrically coupled to the interchangeable source/drain region. After that, the process of etch back is utilized to remove the polysilicon layer 107 on the insulator layer 108.
Then a conductive layer 110 is over the polysilicon layer 107 to be a lower electrode of a capacitor for storing charges. Then, a photoresist layer 112 is defined on the conductive layer 110 to partly expose the conductive layer 110.
The conventional technology of etching to define the conductive layer 110 has two problems as follows:
1. Referring to FIG. 2, if an ion plasma beam with low ion energy, high pressure and low density is applied, then a slanted periphery wall 114 of the conductive layer 110a can be formed. For a DRAM with high integration, a micro-loading 111 is easy to happen between the neighboring capacitors under the etching by the conventional technology. The micro-loading 111 can cause the neighboring capacitors are connected to result in a short of the circuit. Each capacitor is corresponding to one block of conductive layer 110a. To avoid the micro-loading 111, the distance between the neighboring capacitors should be pulled farther but it undermines the high integration for fabricating the DRAM.
2. Referring to FIG. 3, if an ion plasma beam with high ion energy, low pressure and high density is applied, then even though the slanted periphery wall 114 under the etching as described above can be avoided, a fence-like plate 113 between a conductive layer 110b and a photoresist layer 112b can usually happen due to the by-products of the reactions between a metal oxide layer of the conductive layer 110b and the photoresist layer 112b. The fence-like plate 113 is not easy to be removed.
Referring to FIG. 4, after removing the photoresist layer 112b, the fence-like plate 113 is still adhering to the conductive layer 110b. If both the conductive layer 110b and the fence-like plate 113 are treated together directly as the lower electrode. The sharp area 115 on the fence-like plate 113 should cause the leakage current.